Title :
The influence of the drain multiplication current on latchup behavior
Author :
Deferm, Ludo ; Lebon, Hans A. ; Claeys, Cor ; Declerck, Gilbert J.
Author_Institution :
Adv. Semicond. Processing Div., Imec, Leuven, Belgium
fDate :
11/1/1988 12:00:00 AM
Abstract :
A method is described for determining the maximum operating voltage of a NMOS transistor in a CMOS technology before latch-up occurs. The drain multiplication current and the shunting well resistance are very important parameters for simulating the initiation of the parasitic thyristor. Measurement results show the influence of the well resistance and the gate length for transistors processed on bulk wafers and on epi wafers. Good agreement between simulations and experimental results is obtained
Keywords :
CMOS integrated circuits; integrated circuit technology; integrated circuit testing; CMOS technology; NMOS transistor; bulk wafers; drain multiplication current; epi wafers; gate length; latchup behavior; maximum operating voltage; parasitic thyristor; shunting well resistance; simulations; CMOS technology; Electrical resistance measurement; Geometry; Impurities; Length measurement; MOSFETs; Poisson equations; Semiconductor diodes; Thyristors; Voltage;
Journal_Title :
Electron Devices, IEEE Transactions on
