DESSERT: DESign Space ExploRation Tool based on power and energy at System-Level

This paper proposes DESSERT (DESign Space ExploRation Tool at System-Level), a novel simulation-based tool for heterogeneous multi-core processor based platforms. This tool supports power/energy estimation, comprehensive architectural explorations and optimization of the given embedded applications for multi-core processor architectures. The development of DESSERT consists of three steps. First, we developed generic functional-level power models for different parts of the multi-core system to estimate power/energy, which are integrated into the system-level simulation environment. Second, we built a SystemC-based virtual platform prototype of the processor architecture to accurately extract the functional activities needed by the power model. Third, we designed a runtime task-dependencies management and optimization technique (work-load or dynamic slack reclamation) based on programming models that support both OpenMP and Pthread API for multi-core execution to consider both data-level and thread-level parallelism. The combination of above three steps leads to a novel Design Space Exploration (DSE) methodology. Power and energy estimates are validated against real board measurements. DESSERT power/energy estimation results provide less than 5% of error and offer reliable power/energy based DSE for the given applications.