• DocumentCode
    146217
  • Title

    A novel ratioed logic style for faster subthreshold digital circuits based on 90 nm CMOS and below

  • Author

    Weiwei Shi ; Chiu-Sing Choy

  • Author_Institution
    Coll. of Inf. Eng., Shenzhen Univ., Shenzhen, China
  • fYear
    2014
  • fDate
    2-5 Sept. 2014
  • Firstpage
    54
  • Lastpage
    57
  • Abstract
    An innovative logic style is proposed to achieve faster logic propagation in subthreshold operation: the Active Controlled Ratioed Logic (ACRL). It is an complete improvement and optimization from previous ratioed logic styles with pull-up current control and modified branches tailored to very-low supply voltage and ultra-low power. Even without proper control of its load current at the pre-drive stage, the active power of ACRL cells can be suppressed to a comparable magnitude of static CMOS logic cells leakage. General logic cells and complex circuit designs were fabricated in 90 nm CMOS technology. In measurement they are 30-70% faster than those of static and dynamic CMOS styles, and with lower power when the logic activity rises to a certain level.
  • Keywords
    CMOS logic circuits; logic design; ACRL cells; CMOS technology; active controlled ratioed logic; active power; complex circuit designs; dynamic CMOS styles; faster logic propagation; faster subthreshold digital circuits; general logic cells; load current; logic activity; pre-drive stage; pull-up current control; ratioed logic style; size 90 nm; static CMOS logic cells leakage; static CMOS styles; subthreshold operation; CMOS integrated circuits; CMOS technology; Capacitance; Delays; Logic gates; MOS devices; Power supplies;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    System-on-Chip Conference (SOCC), 2014 27th IEEE International
  • Conference_Location
    Las Vegas, NV
  • Type

    conf

  • DOI
    10.1109/SOCC.2014.6948899
  • Filename
    6948899