Design of a 9-bit 1GS/s CMOS folding A/D converter with a boundary error reduction technique

Author

Jongyoon Hwang ; Dongjoo Kim ; Mun-Kyo Lee ; Sun-Phil Nah ; Minkyu Song

Author_Institution

Dept. of Semicond. Sci., Dongguk Univ., Seoul, South Korea

fYear

2014

fDate

2-5 Sept. 2014

Firstpage

83

Lastpage

87

Abstract

In this paper, design of a 9-bit 1GS/s CMOS folding A/D converter with a boundary error reduction technique is described. In order to reduce the asymmetrical boundary error of the folding ADCs, a new circuit is proposed. Further, an enhanced digital architecture is discussed to support the boundary error reduction technique. The fabricated ADC has a novel digital logic to minimize device mismatching and many errors. The chip has been implemented with 1.1V 45nm Samsung CMOS technology. The effective chip area is 2.99mm² and the power dissipation is 120mW. The measured result of SNDR is 45.35dB, when the input frequency is 150MHz at the sampling frequency of 1GHz. The measured INL is within +5LSB/-3LSB and DNL is within +1.5LSB/-1LSB.

Keywords

CMOS digital integrated circuits; analogue-digital conversion; error correction; CMOS folding A-D converter; Samsung CMOS technology; asymmetrical boundary error; boundary error reduction technique; digital logic; enhanced digital architecture; folding ADC; frequency 1 GHz; frequency 150 MHz; power 120 mW; size 45 nm; voltage 1.1 V; word length 9 bit; CMOS integrated circuits; CMOS technology; Encoding; Error correction; Frequency measurement; Power demand; Semiconductor device measurement; CMOS folding ADC; boundary error reduction technique; enhanced digital architecture;

fLanguage

English

Publisher

ieee

Conference_Titel

System-on-Chip Conference (SOCC), 2014 27th IEEE International

Conference_Location

Las Vegas, NV

Type

conf

DOI

10.1109/SOCC.2014.6948904

Filename

6948904