• DocumentCode
    1462619
  • Title

    Foreword: Electrical overstress/electrostatic discharge

  • Author

    Verhaege, Koen G.

  • Author_Institution
    Sarnoff Corporation, Princeton, NJ 08543 USA
  • Volume
    21
  • Issue
    4
  • fYear
    1998
  • Firstpage
    249
  • Lastpage
    249
  • Abstract
    ON-chip electrical overstress (EOS) and electrostatic discharge (ESD) protection is continuing to attract considerable attention as these phenomena are still within the top five of major causes for semiconductor integrated circuit yield losses. From the 1997 EOS/ESD Symposium, sponsored by the ESD Association in cooperation with and the IEEE, September 1997, Santa Clara, CA, we have chosen four papers to be published in this issue.
  • Keywords
    CMOS integrated circuits; VLSI; electrostatic discharge; failure analysis; integrated circuit metallisation; integrated circuit testing; 0.25 micron; CDM tests; ESD performance; HEM tests; TLP tests; device performance; failure mechanism; fully silicided CMOS technology; gate length; homogeneous snapback; retrograde-like well profiles; well profile; Breakdown voltage; CMOS process; CMOS technology; Electronic ballasts; Electrostatic discharge; Failure analysis; Protection; Silicidation; Silicides; Testing;
  • fLanguage
    English
  • Journal_Title
    Components, Packaging, and Manufacturing Technology, Part C, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1083-4400
  • Type

    jour

  • DOI
    10.1109/3476.739173
  • Filename
    739173
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1462619