Very fast transmission line pulsing of integrated structures and the charged device model

Transmission line pulsing (TLP) is well-established for the IV-characterization of electrostatic discharge (ESD)-protection elements. There still is a significant gap between the performance of present TLP-systems and the demands of the charged device model (CDM). A very fast, narrow-pulse (>3.5 ns), high-current TLP (VF-TLP) is designed to reduce this gap. It is feasible to study the pulsed breakdown of gate oxides and to determine at least the quasistatic IV-characteristics of input structures. Gate oxide breakdown is monitored within the first 6 ns of stress. Correlation with CDM (noncontact, nonsocketed) tests and socket discharge model [(SDM) formerly socketed CDM] is achieved in terms of the failure signature. However, the failure thresholds of VF-TLP and CDM/SDM do not correlate due to the different current paths. In the CDM, mobile charge is injected into or coming out of one pin until the full device is at same potential. In the SDM, the full test board is charged and discharged across the device. The VF-TLP current flows between the stress pin and a reference pin for the duration of the square pulse.