DocumentCode :
146275
Title :
Reliability aware logic synthesis through rewriting
Author :
Grandhi, Srimanarayana ; Spagnol, Christian ; Jiaoyan Chen ; Popovici, Emanuel ; Cotafona, Sorin
Author_Institution :
Dept. of Electr. & Electron. Eng., Univ. Coll. Cork, Cork, Ireland
fYear :
2014
fDate :
2-5 Sept. 2014
Firstpage :
274
Lastpage :
279
Abstract :
The low reliability of advanced CMOS devices has become a critical issue that has to be considered in the digital IC design flow. This paper introduces a design time methodology to address and improve the reliability of combinational circuits. The key idea is to employ local transformation rules, a methodology that were extensively used for area, delay, and power optimizations and demonstrate that they can reduce the error probability as well.We propose a set of local transformation rules that enhance the reliability without altering the circuit functionality. This functional rewriting capability, along with a circuit reliability assessment methodology developed in house, enables the integration of the reliability aware analysis and logic optimization algorithm that iteratively transforms the design in order to achieve higher circuit reliability. Experimental results based on simulations performed on MCNC benchmark circuits indicate that method can provide a reliability improvement of up to 7.5%.
Keywords :
CMOS logic circuits; combinational circuits; digital integrated circuits; error statistics; integrated circuit design; integrated circuit reliability; optimisation; rewriting systems; MCNC benchmark circuits; advanced CMOS devices reliability; area optimizations; circuit functionality; combinatorial circuit reliability assessment methodology; delay optimizations; design time methodology; digital IC design flow; error probability reduction; functional rewriting capability; local transformation rules; logic optimization algorithm; power optimizations; reliability aware logic synthesis; Benchmark testing; Error probability; Integrated circuit reliability; Logic gates; Optimization; Simulation; ABC Tool; And-Invert Graphs (AIG); Local Transformation Rules; Optimization; Reliability; Rewriting; Synthesis;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
System-on-Chip Conference (SOCC), 2014 27th IEEE International
Conference_Location :
Las Vegas, NV
Type :
conf
DOI :
10.1109/SOCC.2014.6948940
Filename :
6948940
Link To Document :
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