• DocumentCode
    1462848
  • Title

    Software-implemented EDAC protection against SEUs

  • Author

    Shirvani, Philip P. ; Saxena, Nirmal R. ; McCluskey, Edward J.

  • Author_Institution
    Dept. of Electr. Eng. & Comput. Sci., Stanford Univ., CA, USA
  • Volume
    49
  • Issue
    3
  • fYear
    2000
  • fDate
    9/1/2000 12:00:00 AM
  • Firstpage
    273
  • Lastpage
    284
  • Abstract
    In many computer systems, the contents of memory are protected by an error detection and correction (EDAC) code. Bit-flips caused by single event upsets (SEU) are a well-known problem in memory chips; EDAC codes have been an effective solution to this problem. These codes are usually implemented in hardware using extra memory bits and encoding/decoding circuitry. In systems where EDAC hardware is not available, the reliability of the system can be improved by providing protection through software. Codes and techniques that can be used for software implementation of EDAC are discussed and compared. The implementation requirements and issues are discussed, and some solutions are presented. The paper discusses in detail how system-level and chip-level structures relate to multiple error correction. A simple solution is presented to make the EDAC scheme independent of these structures. The technique in this paper was implemented and used effectively in an actual space experiment. We have observed that SEU corrupt the operating system or programs of a computer system that does not have any EDAC for memory, forcing the system to be reset frequently. Protecting the entire memory (code and data) might not be practical in software. However this paper demonstrates that software-implemented EDAC is a low-cost solution that provides protection for code segments and can appreciably enhance the system availability in a low-radiation space environment
  • Keywords
    aerospace computing; error correction codes; error detection codes; fault tolerant computing; memory architecture; RAM discs; bit-flips; chip-level structures; encoding/decoding circuitry; error detection and correction code; low cost fault tolerance; low-radiation space environment; memory chips; read and write operations; reliability improvement; satellite experiment; secondary storage systems; single event upsets; software implementation; software-implemented EDAC; software-implemented EDAC protection; solid-state memories; system-level structures; Circuits; Computer errors; Decoding; Encoding; Error correction; Error correction codes; Hardware; Protection; Single event transient; Single event upset;
  • fLanguage
    English
  • Journal_Title
    Reliability, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9529
  • Type

    jour

  • DOI
    10.1109/24.914544
  • Filename
    914544