160-Gb/s Optical Packet Switching Subsystem With a Monolithic Optical Phased-Array Switch

Author

Soganci, Ibrahim Murat ; Calabretta, Nicola ; Tanemura, Takuo ; Wang, Wenrui ; Raz, Oded ; Higuchi, Kazuhide ; Williams, Kevin A. ; de Vries, Tjibbe ; Dorren, Harmen Joseph Sebastian ; Nakano, Yoshiaki

Author_Institution

Inf. Devices Lab., Univ. of Tokyo, Tokyo, Japan

Volume

22

Issue

11

fYear

2010

fDate

6/1/2010 12:00:00 AM

Firstpage

817

Lastpage

819

Abstract

1 × 8 and 1 × 16 optical packet switching (OPS) node subsystems are demonstrated. The OPS node consists of a 1 × N monolithically integrated InP optical phased-array switch, an electronic switch controller, and a label extractor/eraser that utilizes cascaded reflective fiber Bragg gratings. In-band parallel labels are employed to encode the address information. 160-Gb/s optical time-domain-multiplexed packets are dynamically switched to 8 and 16 outputs with power penalties of 0.5 and 0.7 dB, respectively.

Keywords

Bragg gratings; optical switches; packet switching; InP; OPS node subsystem; bit rate 160 Gbit/s; cascaded reflective fiber Bragg gratings; electronic switch controller; label eraser; label extractor; monolithically integrated InP optical phased-array switch; optical packet switching subsystem; optical time-domain-multiplexed packet; power penalty; Integrated photonics; optical label swapping; optical packet switching (OPS); phased arrays;

fLanguage

English

Journal_Title

Photonics Technology Letters, IEEE

Publisher

ieee

ISSN

1041-1135

Type

jour

DOI

10.1109/LPT.2010.2046161

Filename

5443598