A unified approach to statistical design centering of integrated circuits with correlated parameters

This paper presents a general method for statistical design centering of integrated circuits with correlated parameters. It unifies worst-case design, nominal design and tolerance design in a single framework by selecting appropriate norms to measure the distances from the nominal values. The method uses an advanced first-order second moment technique as an alternative to the simplicial algorithm. Yield estimation is calculated in the original space and no transformation to uncorrelated variables is required. The solution algorithms are based on the recently developed interior-point methods for semi-definite programming. One tutorial and one practical example explain the application