Title :
A Quad-Band GSM/GPRS/EDGE SoC in 65 nm CMOS
Author :
Darabi, H. ; Chang, Peter ; Jensen, H. ; Zolfaghari, A. ; Lettieri, P. ; Leete, J.C. ; Mohammadi, B. ; Chiu, J. ; Qiang Li ; Shr-Lung Chen ; Zhimin Zhou ; Vadipour, M. ; Chen, Ci ; Yuyu Chang ; Mirzaei, A. ; Yazdi, A. ; Nariman, M. ; Hadji-Abdolhamid, A.
Author_Institution :
Broadcom Corp., Irvine, CA, USA
fDate :
4/1/2011 12:00:00 AM
Abstract :
A quad-band 2.5G SoC integrating all the RF, DSP, ARM, audio and other baseband processing functions into a single 65 nm CMOS die is described. The paper focuses on the radio portion mostly, and addresses the challenges of realizing a complete GSM/EDGE SoC with the RF integrated along with the rest of digital baseband circuitry. Several circuit level as well as architectural techniques are presented to realize a very low-cost and low-power 2.5G radio while meeting the stringent cellular requirements with wide margin. The radio draws a battery current of 49 mA in the receiver-mode, and 86/77 mA in the GMSK/8PSK transmit-mode. The low-IF receiver achieves a sensitivity of -110 dBm at the antenna, corresponding to a noise figure of 2.4 dB at the device input. The 8PSK±400 kHz modulation mask is - 64.1/62.7 dBc for high/low bands, with an RMS EVM of 2.45/1.95%. The radio core area is 3.95 mm2 .
Keywords :
CMOS integrated circuits; cellular radio; mobile handsets; packet radio networks; radio receivers; system-on-chip; CMOS; GSM/GPRS/EDGE SoC; baseband processing functions; digital baseband circuitry; frequency 2.5 GHz; low-IF receiver; quad-band SoC; size 65 nm; Baseband; GSM; Noise; Phase locked loops; Radio frequency; Receivers; System-on-a-chip; 8PSK; CMOS; Cellular; EDGE; EDGE SoC; GMSK; GPRS; GSM; PLL; SoC; crystal oscillator; direct conversion; direct modulation; low IF; polar; submicron CMOS;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2011.2109432
