DocumentCode :
146330
Title :
A 25.5mW 10Gb/s inductorless receiver with an adaptive front-end in 0.13 µm CMOS.
Author :
Monga, Sushrant ; Chatterjee, Saptarshi
Author_Institution :
Cadence AMS Design Syst., Bangalore, India
fYear :
2014
fDate :
2-5 Sept. 2014
Firstpage :
431
Lastpage :
436
Abstract :
An inductorless adaptive wireline receiver is presented with a digital calibration technique to define the frequency response based on the output data-eye. The receiver incorporates a transimpedance amplifier with nested active feedback as the analog front-end for broadband gain. An inductorless peaking technique is described that boosts the gain at the desired frequencies by an additional 5-8 dB. A method for adaptive equalization is described based on output data eye opening consuming very-less power(6% of the total). Measurement results depict the successful equalization of channels having an attenuation of upto -19 dB at 5 GHz. The circuit is fabricated in 0.13 μm CMOS technology and consumes a power of 25.5mW at the operating data rate of 10Gb/s.
Keywords :
CMOS integrated circuits; calibration; equalisers; frequency response; operational amplifiers; optical receivers; CMOS technology; adaptive equalization; adaptive front-end; bit rate 10 Gbit/s; channel equalization; digital calibration technique; frequency response; inductorless adaptive wireline receiver; inductorless peaking technique; nested active feedback; output data-eye; power 25.5 mW; size 0.13 mum; transimpedance amplifier; Calibration; Feedback loop; Frequency response; Gain; Negative feedback; Receivers; Transconductance; Gbps; continuous time equalizer; decision feedback; frequency response; serial link receiver;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
System-on-Chip Conference (SOCC), 2014 27th IEEE International
Conference_Location :
Las Vegas, NV
Type :
conf
DOI :
10.1109/SOCC.2014.6948968
Filename :
6948968
Link To Document :
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