SOI SJ high voltage device with linear variable doping interface thin silicon layer

Author

Wu, L.J. ; Zhang, W.T. ; Qiao, Ming ; Zhang, Boming ; Li, Z.J.

Author_Institution

State key Lab. of Electron. Thin Films & Integrated Devices, UESTC, Chengdu, China

Volume

48

Issue

5

fYear

2012

Firstpage

297

Lastpage

289

Abstract

A novel high concentration linear variable doping interface thin silicon layer (TSL) silicon-on-insulator (SOI) super junction (SJ) LDMOS is proposed. The design of the linear variable doping can deplete the high drift concentration. The proposed structure uses a TSL to achieve charge balance and eliminate substrate-assisted depletion effect. The dielectric electric field (EI) and the breakdown voltage (BV) of the TSL SOI SJ are 530 V/ m and 552 V with 30 m length drift region and 1 m-thick dielectric layer, respectively, and the specific on-resistance (Ron, sp) is 0.03403 cm² and FOM (FOM=BV²/Ron,sp) is 8.95 MW/cm², when gate voltage is 5 V.

Keywords

MIS devices; dielectric materials; elemental semiconductors; semiconductor doping; silicon; silicon-on-insulator; SOI SJ high-voltage device; Si; breakdown voltage; charge balance; dielectric electric field; dielectric layer; drift concentration; drift region; linear-variable doping interface TSL; silicon-on-insulator super-junction LDMOS; size 1 m; size 30 m; substrate-assisted depletion effect; thin-silicon layer; voltage 5 V; voltage 552 V;

fLanguage

English

Journal_Title

Electronics Letters

Publisher

iet

ISSN

0013-5194

Type

jour

DOI

10.1049/el.2011.3437

Filename

6164332