Title :
Limits of integrated-circuit manufacturing
Author :
Doering, Robert ; Nishi, Yoshio
Author_Institution :
Texas Instrum. Inc., Dallas, TX, USA
fDate :
3/1/2001 12:00:00 AM
Abstract :
A methodology is suggested for the study of integrated-circuit manufacturing limits. It is based on a hierarchical view of manufacturing detractors and associates limits with levels in this hierarchy. The methodology is illustrated with examples of steady-state, theoretical, and process limits at today´s state of the art as well as example projections to future manufacturing at what may be near the limits of complementary metal-oxide-semiconductor (CMOS) scaling. There are also some speculations on possibilities beyond these limits
Keywords :
CMOS integrated circuits; integrated circuit manufacture; reviews; CMOS scaling; IC manufacturing limits; integrated circuit manufacturing; process limits; CMOS process; Circuits; Costs; Instruments; Manufacturing processes; Material properties; Pulp manufacturing; Semiconductor device manufacture; Semiconductor devices; Steady-state;
Journal_Title :
Proceedings of the IEEE
