Realization of Gmicro/200

Author

Inayoshi, Hideo ; Kawasaki, Ikuya ; Nishimukai, Tadahiko ; Sakamura, Ken

Author_Institution

Hitachi Ltd., Tokyo, Japan

Volume

8

Issue

2

fYear

1988

fDate

4/1/1988 12:00:00 AM

Firstpage

12

Lastpage

21

Abstract

The Gmicro/200, a microprocessor that has been developed as part of Japan´s TRON (The Real-Time Operating Nucleus) project, is described. This microprogram-based processor with six-state pipeline, 730000 transistors and on-chip caches will serve in an engineering workstation or a high-speed graphics accelerator system. The authors discuss features of the instruction set; memory management; handling of exceptions, interrupts and traps; and the implementation of the Gmicro/200.<>

Keywords

instruction sets; interrupts; microprocessor chips; microprogramming; real-time systems; research initiatives; storage management chips; Gmicro/200; Hitachi; Japan; TRON; The Real-Time Operating Nucleus; VSLI; engineering workstation; exception handling; high-speed graphics accelerator; instruction set; interrupt handling; memory management; microprogram-based processor; on-chip caches; six-state pipeline; trap handling; Computer architecture; Coprocessors; Graphics; Memory management; Microprocessors; Pipelines; Registers; System-on-a-chip; Very large scale integration; Workstations;

fLanguage

English

Journal_Title

Micro, IEEE

Publisher

ieee

ISSN

0272-1732

Type

jour

DOI

10.1109/40.526

Filename

526