A high-performance bipolar/CMOS process-CIT2

A novel self-aligned bipolar/CMOS process called Collector Implanted Technology 2 (CIT2) with 1.5-μm optical lithography has been developed. LSI chips fabricated in standard bipolar technologies with high-temperature processes, which have buried layer, epitaxy, and isolation diffusions, have a reduced yield compared to MOS circuits and are difficult to combine with CMOS. Therefore a new process with an implanted collector was developed. CIT technology uses neither epitaxy nor a buried layer. It can be produced on a bipolar or MOS production line. n-p-n transistors with a high transition frequency (f_T=5 GHz) and ECL gates with a delay time of 180 ps were made. The complete surface of the extrinsic base is covered with platinum silicide, and thus its resistance is reduced to a value of 20 Ω. The performance of the n- and p-channel MOS transistors is comparable to those of a conventional CMOS process. The p-channel MOS transistors is formed in an n-well. The drain and source both p- and n-channel, direct contacted by polysilicide. The minimum propagation delay is 280 ps