Title :
Comprehensive and Accurate Parasitic Capacitance Models for Two- and Three-Dimensional CMOS Device Structures
Author :
Lacord, Joris ; Ghibaudo, Gérard ; Boeuf, Frédéric
Author_Institution :
STMicroelectron., Crolles, France
fDate :
5/1/2012 12:00:00 AM
Abstract :
In this paper, we propose an accurate, detailed, and ready-to-use model to evaluate quickly parasitic capacitances on several CMOS architectures: planar bulk, planar FDSOI, planar double gate (DG), and FinFET (in DG or triple-gate configuration). This model takes into account raised source drain, trench contacts and discreet contacts, bilayer spacers, and inner-fringe capacitance screening. It has been validated with 2-D (FlexPDE software) and 3-D (Raphael software) simulations.
Keywords :
CMOS integrated circuits; MOSFET; semiconductor device models; three-dimensional integrated circuits; 2D simulations; 3D simulations; FinFET; accurate parasitic capacitance models; bilayer spacers; comprehensive parasitic capacitance models; discreet contacts; inner-fringe capacitance screening; planar FDSOI; planar double gate; source drain; three-dimensional CMOS device structures; trench contacts; two-dimensional CMOS device structures; Capacitance; Junctions; Logic gates; Mathematical model; Mercury (metals); Numerical models; Semiconductor device modeling; Analytical model; CMOS; benchmarking; parasitic capacitance;
Journal_Title :
Electron Devices, IEEE Transactions on
DOI :
10.1109/TED.2012.2187454
