Technology and device scaling considerations for CMOS imagers

Author

Wong, Hon-Sum

Author_Institution

IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA

Volume

43

Issue

12

fYear

1996

fDate

12/1/1996 12:00:00 AM

Firstpage

2131

Lastpage

2142

Abstract

This paper presents an analysis of the impact of device and technology scaling on active pixel CMOS image sensors. Using the SLA roadmap as a guideline, we calculate the device characteristics that are germane to the image sensing performance of CMOS imagers, and highlight the areas where the CIMOS imager technology may need to depart from “standard” CMOS technologies. The impact of scaling on those analog circuit performance that pertain to image sensing performances are analyzed. Our analyses suggest that while “standard” CMOS technologies may provide adequate imaging performance at the 2-1 μm generation without any process change, some modifications to the fabrication process and innovations of the pixel architecture are needed to enable CMOS to perform good quality imaging at the 0.5 μm technology generation and beyond. Finally, the challenges to the CMOS imager research community are outlined

Keywords

CMOS analogue integrated circuits; image sensors; integrated circuit technology; 0.5 micron; 2 to 1 micron; SLA roadmap; active pixel CMOS image sensor; analog circuit; device scaling; fabrication; pixel architecture; technology; Analog circuits; CMOS image sensors; CMOS process; CMOS technology; Fabrication; Guidelines; Image analysis; Performance analysis; Pixel; Technological innovation;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.544384

Filename

544384