• DocumentCode
    1464592
  • Title

    A generic methodology for deriving compact dynamic thermal models, applied to the PSGA package

  • Author

    Christiaens, Filip ; Vandevelde, Bart ; Beyne, Eric ; Mertens, Robert ; Berghmans, Jan

  • Author_Institution
    Materials and Packaging Division, IMEC, Leuven B-3001, Belgium; Switching Systems Division, Alcatel Telecom, Antwerpen B-2018, Belgium
  • Volume
    21
  • Issue
    4
  • fYear
    1998
  • Firstpage
    565
  • Lastpage
    576
  • Abstract
    A novel methodology for synthesizing compact, boundary condition independent, dynamic thermal models is represented. The resulting compact resistor/capacitor network accurately predicts the dynamic junction temperature response under any arbitrary set of external cooling conditions. The network is derived in two successive steps. First, a boundary condition independent resistor network is synthesized using steady-state finite element data for a large set of practical boundary conditions. Next, the general resistor network is expanded with discrete thermal capacitors featuring the thermal mass of the package. The value of the capacitors and their exact location within the resistor network is determined using frequency response finite element data for a limited set of boundary conditions. This paper focuses primarily on the second step, i.e., synthesis of the dynamic (capacitive) network elements. The synthesis method is successfully demonstrated for two types of polymer stud grid array (PSGA) packages, the standard PSGA and the thermally enhanced PSGA. It is shown that the thermal mass of a PSGA package can be lumped into five discrete thermal capacitances. For both the standard and the thermally enhanced PSGA, the generic compact dynamic network models can predict time dependent junction temperature profiles within an accuracy of 5%.
  • Keywords
    atomic force microscopy; failure analysis; focused ion beam technology; lead bonding; AFM; Al-Si; BOE etching; EDX; FIB; SEM; bond pad metal peeling; failure analysis; polysilicon surface roughness asperity; reliability; semiconductor chip; wire bonding; yield; Atherosclerosis; Atomic force microscopy; Bonding; Etching; Failure analysis; Rough surfaces; Scanning electron microscopy; Surface roughness; Very large scale integration; Wire; Compact models; dynamic behavior; packaging; polymer stud grid array; thermal management;
  • fLanguage
    English
  • Journal_Title
    Components, Packaging, and Manufacturing Technology, Part A, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1070-9886
  • Type

    jour

  • DOI
    10.1109/95.740049
  • Filename
    740049