A novel SCR ESD protection for triple well CMOS technologies

Author

Nikolaidis, T. ; Papadas, C.

Author_Institution

ISD S.A., Athens, Greece

Volume

22

Issue

4

fYear

2001

fDate

4/1/2001 12:00:00 AM

Firstpage

185

Lastpage

187

Abstract

A novel SCR structure for on-chip ESD protection implemented with a deep submicron triple well CMOS technology is presented. The triple well technology offers the possibility of biasing the p-well, on which the structure is built, under transient ESD stress conditions and independently from the substrate. This greatly affects the turn on mechanism of the structure. Unlike conventional SCR devices, the proposed p-well coupled SCR offers a reduced triggering voltage level as well as the enhanced ESD performance of the SCR devices. The turn on of this structure is realized with a common RC trigger network. The concept is supported by device simulation results.

Keywords

CMOS integrated circuits; electrostatic discharge; integrated circuit reliability; overvoltage protection; thyristor applications; trigger circuits; 0.18 mum; RC trigger network; SCR ESD protection; SCR structure; body coupling; deep submicron triple well CMOS technology; device simulation; on-chip ESD protection; p-well biasing; silicon controlled rectifier; transient ESD stress conditions; triggering voltage level; triple well CMOS technologies; turn on mechanism; CMOS process; CMOS technology; Coupling circuits; Electrostatic discharge; MOSFETs; Protection; Silicon; Stress; Thyristors; Voltage;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/55.915608

Filename

915608