Modeling of the parasitic transistor-induced drain breakdown in MOSFETs

Author

Wong, Hei

Author_Institution

Dept. of Electron. Eng., City Univ. of Hong Kong, Kowloon, Hong Kong

Volume

43

Issue

12

fYear

1996

fDate

12/1/1996 12:00:00 AM

Firstpage

2190

Lastpage

2196

Abstract

Parasitic bipolar transistor (PET) induced breakdown characteristics in MOSFETs are investigated and modeled with the aid of MINIMOS simulation. Formula for approximating the breakdown voltage is also developed. The proposed model agrees well with the MINIMOS simulation results, especially in the bias, temperature, and substrate resistance dependencies. According to the simulation and theoretical results, the breakdown voltage for the PET-induced breakdown can be increased by raising the temperature, increasing the channel length, and reducing the substrate resistance

Keywords

MOSFET; electric breakdown; semiconductor device models; MINIMOS simulation; MOSFET; breakdown characteristics; breakdown voltage approximation; channel length; parasitic bipolar transistor; parasitic transistor-induced drain breakdown; substrate resistance; Avalanche breakdown; Bipolar transistors; Breakdown voltage; Charge carrier processes; Cities and towns; Current measurement; Electric breakdown; Electrons; Impact ionization; MOSFET circuits; MOSFETs; Positron emission tomography; Temperature dependence; Thermal resistance;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.544391

Filename

544391