Determination and assessment of the floating-body voltage of SOI CMOS devices

A self-consistent method to extract the off-state floating-body (FB) voltage of SOI CMOS devices is presented. The technique is simple and is based on CV and S-parameter measurements of a single standard SOI MOSFET device; no special test structure design is needed. The bias dependent S-parameter measurements of the FB SOI device and its equivalent circuit, along with the CV measurements between the drain and source of the same device, are used to determine the FB voltage. The technique provides reasonable insight on device off-state and leakage performances that are important for digital applications. Additionally, it proposes a method for the extraction of the parasitic source, drain, and gate resistances. Using the technique, FB voltage in excess of 0.4 V is measured in a partially depleted (PD) NMOS device at drain voltage of 2.5 V and zero gate voltage, demonstrating the importance of understanding FB effects on device off-state and junction leakage performances