Title :
Probabilistically Programmed STT-MRAM
Author :
Wu, Wenqing ; Zhu, Xiaochun ; Kang, Seung ; Yuen, Kendrick ; Gilmore, Rob
Author_Institution :
Corp. R & D Div., Qualcomm Inc., San Diego, CA, USA
fDate :
3/1/2012 12:00:00 AM
Abstract :
Novel memory programming methods and corresponding memory structures are presented in this paper. Unlike conventional memory programming, this programming technique does not require deterministic switching of memory elements. This technique explicitly exploits the probabilistic switching characteristics of memory elements such as spin-transfer torque magnetic tunnel junction (STT-MTJ) to reduce programming power and delay. This technique also allows multilevel cell (MLC) spin-transfer torque magnetoresistive random access memory (STT-MRAM) to be fabricated with existing STT-MTJ fabrication processes, thus making high capacity STT-MRAM chips readily achievable. The optimal STT-MTJ switching probabilities are given in this paper for reaching minimum programming delay, power, and iteration. Moreover, this paper proves, by applying probabilistic programming to existing STT-MTJs, both programming delay and power can be reduced to levels beyond the reach of conventional deterministic programming. Furthermore arbitrarily small programming bit error rate (BER) can be accomplished in theory using probabilistic programming without much penalty on average programming delay and power. On the contrary, deterministic programming always presents finite programming BER, which is expensive to reduce in terms of programming power and delay. The MLC capability of STT-MTJ clusters has also been confirmed using fabricated STT-MTJ devices. The major circuitries for implementing probabilistically programmed MLC STT-MRAM are also presented in this paper.
Keywords :
MRAM devices; error statistics; magnetic tunnelling; MLC STT-MRAM; STT-MRAM chips; STT-MTJ fabrication process; deterministic programming; finite programming BER; memory element probabilistic switching characteristics; memory programming methods; memory structures; multilevel cell STT-MRAM; optimal STT-MTJ switching probabilities; probabilistically-programmed STT-MRAM; programming bit error rate; programming delay; programming power; spin-transfer torque magnetic tunnel junction; spin-transfer torque magnetoresistive random access memory; Bit error rate; Clustering algorithms; Delay; Monte Carlo methods; Probabilistic logic; Programming; Switches; Arbitrarily small programming bit error rate (BER); high capacity spin-transfer torque magnetoresistive random access memory (STT-MRAM) chips; low power STT-MRAM; multilevel cell (MLC) memory; probabilistic programming; stochastic switching;
Journal_Title :
Emerging and Selected Topics in Circuits and Systems, IEEE Journal on
DOI :
10.1109/JETCAS.2012.2187401