Programmable canonical switched-capacitor bump equaliser architecture

A digitally programmable switched-capacitor (SC) bump equaliser structure is presented. It can operate with two non-overlapping clock phases and uses two overlapping clock phases, two operational amplifiers and eight capacitor banks to control the central frequency, the bandwidth and the peak voltage gain steps of the bump (and dip) frequency responses. In the design method, the programmable capacitor arrays are tailored to provide exactly the capacitance values required to realise a restricted but useful set of frequency responses. As a result, the performance of the proposed SC equaliser is not sacrificed for programmability. Numerical results are reported to confirm the viability of the proposed design method