DocumentCode :
1465587
Title :
Tunable Replica Bits for Dynamic Variation Tolerance in 8T SRAM Arrays
Author :
Raychowdhury, Arijit ; Geuskens, Bibiche M. ; Bowman, Keith A. ; Tschanz, James W. ; Lu, Shih-Lien L. ; Karnik, Tanay ; Khellah, Muhammad M. ; De, Vivek K.
Author_Institution :
Circuits Res. Lab., Intel Corp., Hillsboro, OR, USA
Volume :
46
Issue :
4
fYear :
2011
fDate :
4/1/2011 12:00:00 AM
Firstpage :
797
Lastpage :
805
Abstract :
Infrequent dynamic events like VCC droops and temperature changes result in the use of a static VCC guardband in 8T SRAM arrays. This paper proposes the use of tunable replica bits (TRBs) as a potential solution to mitigating a part of the VCC guardband. Measured data on a 16 KB 8T array featuring tun able replica bits illustrate 9% reduction of the operating minimum VCC (VMIN) and correspondingly a 7.5% reduction in array power.
Keywords :
SRAM chips; 8T SRAM arrays; dynamic variation tolerance; tunable replica bits; Calibration; Computer architecture; Microprocessors; Noise; Random access memory; Timing; Tuning; 8T SRAM arrays; dynamic variations; error detection; resilient circuits; resilient design; resilient memory; resilient microprocessor; timing error; tunable replica bits;
fLanguage :
English
Journal_Title :
Solid-State Circuits, IEEE Journal of
Publisher :
ieee
ISSN :
0018-9200
Type :
jour
DOI :
10.1109/JSSC.2011.2108141
Filename :
5724257
Link To Document :
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