Title :
A new synchronizer design
Author :
Walker, Jacqueline ; Cantoni, Antonio
Author_Institution :
Australian Telecom. Res. Inst., Curtin Univ. of Technol., Bentley, WA, Australia
fDate :
11/1/1996 12:00:00 AM
Abstract :
A new synchronizer design is presented. Current synchronizer designs have certain disadvantages, both in characterization and in the tradeoff between settling time and sampling rate, which are overcome in the new design. Two possible implementations of the synchronizer are discussed
Keywords :
asynchronous circuits; logic design; signal processing; synchronous digital hierarchy; sampling rate; settling time; synchronizer design; Broadcasting; Degradation; Digital systems; Distributed computing; Fault diagnosis; Fault tolerance; Hypercubes; Proposals; Routing; Signal design;
Journal_Title :
Computers, IEEE Transactions on
