• DocumentCode
    1466183
  • Title

    Symmetric Varactor in 130-nm CMOS for Frequency Multiplier Applications

  • Author

    Shim, Dongha ; Kenneth, K.O.

  • Author_Institution
    Electr. & Comput. Eng. Dept., Univ. of Florida, Gainesville, FL, USA
  • Volume
    32
  • Issue
    4
  • fYear
    2011
  • fDate
    4/1/2011 12:00:00 AM
  • Firstpage
    470
  • Lastpage
    472
  • Abstract
    A symmetric varactor (SVAR) in 130-nm digital complementary metal-oxide-semiconductor (CMOS) for frequency multiplier applications with the maximum cutoff frequency of ~320 GHz and a dynamic cutoff frequency of ~125 GHz is demonstrated. To demonstrate the generation of odd-order harmonics and suppression of even-order ones, an SVAR was measured at the pumping frequency of 900 MHz. The measured third-order harmonic power is more than 25 dB higher than that for the second order. Harmonic balance simulations showed that the SVAR pumped by a 50-GHz signal source can generate a 150-GHz third-harmonic output signal with 15.8-dB minimum conversion loss at the input power of 7.8 dBm. The SVAR can be integrated with other (CMOS) components to generate millimeter-wave signals.
  • Keywords
    CMOS integrated circuits; frequency multipliers; varactors; CMOS; frequency multiplier applications; harmonic balance simulations; millimeter-wave signals; size 130 nm; symmetric varactor; third-order harmonic power; CMOS integrated circuits; Capacitance; Cutoff frequency; Harmonic analysis; Power system harmonics; Radio frequency; Varactors; Accumulation mode; complementary metal–oxide–semiconductor (CMOS); frequency multiplier; millimeter wave; symmetric varactor (SVAR);
  • fLanguage
    English
  • Journal_Title
    Electron Device Letters, IEEE
  • Publisher
    ieee
  • ISSN
    0741-3106
  • Type

    jour

  • DOI
    10.1109/LED.2011.2108994
  • Filename
    5725160