Title :
Accelerating Parallel Computations with OpenMP-Driven System-on-Chip Generation for FPGAs
Author_Institution :
Sch. of Inf. & Commun. Technol., R. Inst. of Technol. (KTH), Stockholm, Sweden
Abstract :
The task-based programming paradigm offers a portable way of writing parallel applications. However, it requires tedious tuning of the application for performance. We present a novel design flow where programmers can use application knowledge to easily generate a System-on-Chip (SoC) specialized in executing the application. Our design flow uses a compiler that automatically generates task-specific cores and packs them into a custom SoC. A SoC-specific runtime systems schedules tasks on cores to accelerate application execution. The generated SoC shows up to 6000 times performance improvement in comparison to the Altera NiosII/s processor and up to 7 times compared to an AMD Opteron 6172 core. Our design flow helps programmers generate high-performance systems without requiring tuning and prior hardware design knowledge.
Keywords :
field programmable gate arrays; integrated circuit design; parallel processing; system-on-chip; AMD Opteron 6172 core; Altera NiosII-s processor; FPGA; OpenMP-driven system-on-chip generation; application execution; application knowledge; custom SoC; design flow; high-performance systems; parallel computations; performance improvement; specific runtime systems; task-based programming paradigm; task-specific cores; Field programmable gate arrays; Hardware; Kernel; Parallel processing; Registers; System-on-chip; HLS; Hardware Generation; OpenMP FPGA; Parallel; Software-Hardeware; Task-based;
Conference_Titel :
Embedded Multicore/Manycore SoCs (MCSoc), 2014 IEEE 8th International Symposium on
Conference_Location :
Aizu-Wakamatsu
DOI :
10.1109/MCSoC.2014.30