SAMNoC: A Novel Optical Network-on-Chip for Energy-Efficient Memory Access

Thanks to recent progresses in optical device integration, nanophotonic interconnect can be applied to build optical network-on-chip (ONoC) for providing connectivity among increasing number of cores and memory modules in future many-core processors. However, there are still challenges in architecture and protocol design of ONoC for massive parallel memory accesses in CMPs, The on-chip memory access traffic exhibits heterogeneity for different nodes, i.e. Cores and memory controllers and different memory packets. This paper analyses on-chip communication characteristics and proposes a novel ONoC named SAMNoC. In SAMNoC, memory controllers are able to make self-arbitration for network resources to support node heterogeneity, and different packets are transmitted in dedicated sub-networks to optimize memory traffic. The memory request sub-network applies efficient global communication via slot and coded tokens to exploit bank level parallelism and the response sub-network can eliminate network bottleneck and process memory transactions quickly when the data is ready. Simulation results on real applications show that our SAMNoC can significantly improve memory performance, compared with other bus-based ONoC alternatives, with lower static power consumption and less number of optical waveguides and micro-rings.