• DocumentCode
    146648
  • Title

    A Cache Aware Multithreading Decision Scheme on GPGPUs

  • Author

    Ta Kang Yen ; Bo-Yao Yu ; Lai, Bo Cheng Charles

  • Author_Institution
    Electron. Eng. Dept., Nat. Chiao-Tung Univ., Hsinchu, Taiwan
  • fYear
    2014
  • fDate
    23-25 Sept. 2014
  • Firstpage
    267
  • Lastpage
    272
  • Abstract
    GPGPUs have emerged as one of the most widely used throughput processors. Deep multithreading and on-chip cache hierarchy are the two effective designs to achieve high throughput computing in modern GPGPUs. However, excessive multithreading could aggravate the cache contention while conservative multithreading could leave the execution resource under-utilized. Finding a proper design point between the two has become a significant performance factor to GPGPUs. This paper investigates the correlation between caching behavior and multithreading technique. By demonstrating the trade-off issue between the multithreading and cache contention, this paper proposes a multithreading decision scheme to dynamically adjusts the multithreading degree to achieve superior performance. With the proposed decision scheme, the system performance of memory-intensive workloads can be improved by 60% in average.
  • Keywords
    cache storage; graphics processing units; multi-threading; GPGPUs; cache aware multithreading decision scheme; cache contention; caching behavior; deep multithreading; memory-intensive workloads; multithreading degree; multithreading technique; on-chip cache hierarchy; system performance; throughput processors; Bandwidth; Benchmark testing; Memory management; Multithreading; Pipelines; Random access memory; GPGPU; Memory performance; design and optimization; multithreading;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Embedded Multicore/Manycore SoCs (MCSoc), 2014 IEEE 8th International Symposium on
  • Conference_Location
    Aizu-Wakamatsu
  • Type

    conf

  • DOI
    10.1109/MCSoC.2014.45
  • Filename
    6949481