DocumentCode :
146651
Title :
An FPGA-Based Tightly Coupled Accelerator for Data-Intensive Applications
Author :
Yoshimi, Masato ; Kudo, Riichi ; Oge, Yasin ; Terada, Yuki ; Irie, Hidetsugu ; Yoshinaga, Tsunehiro
Author_Institution :
Grad. Sch. of Inf. Syst., Univ. of Electro-Commun., Chofu, Japan
fYear :
2014
fDate :
23-25 Sept. 2014
Firstpage :
289
Lastpage :
296
Abstract :
Computation beside a data source plays an important role in achieving a high performance with low energy consumption in Big Data processing. In contrast to that of a conventional workload, the processing of Big Data frequently requires that a massive amount of data in distributed storage be scanned. A key technique for reducing energy-consuming processor loads is to install a reconfigurable accelerator that is tightly coupled to a computational resource with interfaces. The accelerator is capable of configuring application-specific hardware modules to allow some logical and arithmetic operations for data stream transmission between interfaces, as well as the offloading of control protocols for communication with other computing nodes or storage. In this paper, an FPGA-based accelerator, which is directly attached to DRAM, the network, and storage, is proposed in order to realize an energy efficient computing system. A simple application that counts the words appearing in the data is implemented to evaluate a prototype system. As the accelerator outperforms by 80.66 to 429 times similar applications executed on an SSD-based Hadoop framework, we confirm that the accelerator´s utilization for Big Data processing is beneficial.
Keywords :
Big Data; field programmable gate arrays; power aware computing; Big Data processing; DRAM; FPGA-based tightly coupled accelerator; SSD-based Hadoop framework; application-specific hardware modules; arithmetic operations; control protocols; data stream transmission; data-intensive applications; distributed storage; energy efficient computing system; energy-consuming processor load reduction; logical operations; low energy consumption; Arrays; Ash; Big data; Field programmable gate arrays; Random access memory; Registers; Throughput; Big Data processing; FPGA-based tightly-coupled accelerator; Simple Word Counting;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Embedded Multicore/Manycore SoCs (MCSoc), 2014 IEEE 8th International Symposium on
Conference_Location :
Aizu-Wakamatsu
Type :
conf
DOI :
10.1109/MCSoC.2014.47
Filename :
6949484
Link To Document :
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