Adaptive V-Set Cache for Multi-core Processors

Development in VLSI design allows multi-to many-cores to be integrated on a single microprocessor chip. This increase in the core count per chip makes it more critical to design an efficient memory sub-system especially the Last Level Cache (LLC). The efficient utilization of the LLC is a dominant factor to achieve the best microprocessor throughput due to the increasing gap between processor speed and memory speed. In this paper the author proposes distributed shared v-set cache design that allows an adaptive and dynamic utilization of the cache blocks across the cores while keeps the h/w complexity, which reflects on the system scalability, matching the partitioned design. On four-core microprocessor, the proposed distributed-shared v-set cache design can achieve a maximum speedup of 25%, 15%, and 21% and an average speedup of 12%, 5%, and 9% compared to conventional partitioned private cache, monolithic shared cache, and private/shared NUCA cache designs respectively.