Jitter in digital networks

The accumulation and tolerance of timing jitter in digital networks is analysed for transmission links containing regenerators as well as dejitterizers and/or multiplexer¿demultiplexer pairs, and for timing circuits employing phase-locked-loops. Both systematic pattern-dependent jitter and waiting-time jitter are taken into account. It is shown that, under practical circumstances, the total accumulated jitter can be adequately described by some simple equations and measurement data confirm these equations. An experimental relation between peak-peak jitter values over a long period and those over a short period is presented. The results of the analysis have led to the conclusion that the internationally recommended maximum permissible peak-peak jitter values at digital interfaces will never be reached in the Dutch digital network.