DocumentCode
1466984
Title
RF Characterization and Analytical Modelling of Through Silicon Vias and Coplanar Waveguides for 3D Integration
Author
Lamy, Yann P R ; Jinesh, K.B. ; Roozeboom, Fred ; Gravesteijn, Dirk J. ; Besling, Wim F A
Author_Institution
NXP Semicond. Res., Eindhoven, Netherlands
Volume
33
Issue
4
fYear
2010
Firstpage
1072
Lastpage
1079
Abstract
High-aspect ratio (12.5) through silicon vias (TSV) made in a silicon interposer have been electrically characterized in the direct current (dc) and microwave regimes for 3D interconnect applications. The vias were micro-machined in silicon, insulated, and filled with copper employing a bottom-up copper electroplating technique in a “via-first” approach. DC via resistance measurements show good agreement with the theoretical expected value (~ 16 mΩ) . Radio-frequency (RF) measurements up to 50 GHz have been performed on coplanar waveguides located on the back-side of the wafers and connected to the front-side with TSVs. The S-parameters indicate clearly the beneficial impact of double sided ground planes of the RF signals. The via resistance extracted from impedance measurements is in good agreement with dc values, while the inductance (53 pH) and capacitance (2.4 pF) of the TSV are much lower than conventional wire bonding, which makes the use of TSV very promising for 3D integration. An advanced analytical model is proposed for the interconnect system with vias and lines and shows very good agreement with the experimental data with a limited number of fitting parameters. This work gives a proof of concept for high aspect ratio TSV manufacturing and new insights to improve 3D interconnect modeling for systems-in-package applications in the microwave regime.
Keywords
coplanar waveguides; electroplating; integrated circuit interconnections; radiofrequency integrated circuits; system-in-package; three-dimensional integrated circuits; 3D integration; 3D interconnect application; 3D interconnect modeling; RF characterization; RF signal; Si; analytical modelling; bottom-up copper electroplating technique; coplanar waveguide; high aspect ratio TSV manufacturing; high aspect ratio through silicon vias; impedance measurement; interconnect system; micro-machined in silicon; radio frequency measurement; silicon interposer; systems-in-package application; via resistance measurement; wire bonding; Analytical models; Coplanar waveguides; Copper; Electrical resistance measurement; Impedance measurement; Insulation; Performance evaluation; Radio frequency; Silicon; Through-silicon vias; RF modeling; Radio-frequency (RF) characterisation; Si interposer; TSV; three-dimensional interconnects; through silicon via; through-wafer interconnect; vias;
fLanguage
English
Journal_Title
Advanced Packaging, IEEE Transactions on
Publisher
ieee
ISSN
1521-3323
Type
jour
DOI
10.1109/TADVP.2010.2046166
Filename
5445035
Link To Document