Title :
1.3 V single-stage CMOS opamp
Author :
Lu, G.N. ; Sou, G.
Author_Institution :
Lab. des Instrum. et Syst., Univ. Pierre et Marie Curie, Paris, France
fDate :
10/29/1998 12:00:00 AM
Abstract :
A low-voltage, single-stage opamp realised using a conventional CMOS process is proposed. It was designed by using novel regulated-cascode transistors which have a lower output compliance voltage. A gain-enhancement active load has been built by using a bias-stabilising technique. It enables the opamp to achieve a DC gain of >68 dB with a reduction in supply voltage to ~1.3 V
Keywords :
CMOS analogue integrated circuits; low-power electronics; operational amplifiers; 1.3 V; 68 dB; DC gain; active load; bias stabilisation; low-voltage single-stage CMOS opamp; output compliance voltage; regulated-cascode transistor;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19981436
