Title :
A 22-ns 1-Mbit CMOS high-speed DRAM with address multiplexing
Author :
Lu, Nicky C C ; Bronner, Gary B. ; Kitamura, Koji ; Scheuerlein, Roy E. ; Henkels, Walter H. ; Dhong, Sang H. ; Katayama, Yasunao ; Kirihata, Toshiaki ; Niijima, Hideto ; Franch, Robert L. ; Wang, W. ; Nishiwaki, Motoo ; Pesavento, Frank L. ; Rajeevakumar
Author_Institution :
IBM Res. Div., Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
fDate :
10/1/1989 12:00:00 AM
Abstract :
Describes a 1-Mbit high-speed DRAM (HSDRAM), which has a nominal random access time of less than 27 ns and a column access time of 12 ns with address multiplexing. A double-polysilicon double-metal CMOS technology having PMOS arrays inside n-wells was developed with an average 1.3- mu m feature size. The chip has also been fabricated in a 0.9*shrunken version with an area of 67 mm2, showing a 22-ns access time. The chip power consumption is lower than 500 mW at 60-ns cycle time. This HSDRAM, which provides SRAM-like speed while retaining DRAM-like density, allows DRAMs to be used in a broad new range of applications.
Keywords :
CMOS integrated circuits; VLSI; integrated circuit technology; integrated memory circuits; random-access storage; 1 Mbit; 1.3 micron; 22 ns; 500 mW; 60 ns; CMOS; HSDRAM; PMOS arrays; SRAM-like speed; address multiplexing; column access time; double-polysilicon double-metal CMOS technology; feature size; high-speed DRAM; power consumption; random access time; shrunken version; Aluminum; Boron; CMOS technology; Circuits; Energy consumption; Laboratories; MOS devices; Random access memory; Testing; Voltage; Wiring;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.1989.572579
