Title :
A 1.5-V DRAM for battery-based applications
Author :
Aoki, Masakazu ; Etoh, Jun ; Itoh, Kiyoo ; Kimura, Shin-ichiro ; Kawamoto, Yoshifumi
Author_Institution :
Central Res. Lab., Hitachi Ltd., Tokyo, Japan
fDate :
10/1/1989 12:00:00 AM
Abstract :
Circuit techniques for 1.5-V CMOS DRAMS to be used in battery-based applications are presented. A three-level word pulse and a plate pulse are used to maintain the stored voltage in a memory cell, in spite of the minimized data-line voltage swing for reducing power dissipation. A 3.4- mu m2 data-line shielded stacked capacitor (STC) cell is also proposed to enhance signal-to-noise ratio (SNR) in the memory cell array. The 1.5-V read/write operation is observed successfully through a 2-kbit test device. The data-holding time and alpha -particle-induced soft error rate of the device indicate that the possible performances for the 1.5-V DRAM are comparable to those for the existing 5-V DRAMs.
Keywords :
CMOS integrated circuits; VLSI; alpha-particles; integrated circuit technology; integrated memory circuits; random-access storage; 1.5 V; 2 kbit; 2-kbit test device; CMOS; DRAM; SNR; STC; alpha particle induced error rate; battery-based applications; data-holding time; data-line shielded stacked capacitor; performances; plate pulse; reducing power dissipation; signal-to-noise ratio; soft error rate; three-level word pulse; Batteries; CMOS memory circuits; CMOS technology; Capacitors; Circuits; Energy consumption; Error analysis; Power dissipation; Pulse amplifiers; Random access memory; Read-write memory; Signal to noise ratio; Testing; Threshold voltage; Voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.1989.572581
