A 9-ns 1-Mbit CMOS SRAM

Author

Sasaki, Katsuro ; Ishibashi, Koichiro ; Yamanaka, Toshiaki ; Hashimoto, Naotaka ; Nishida, Takashi ; Shimohigashi, Katsuhiro ; Hanamura, Shoji ; Honjo, Shigeru

Author_Institution

Central Res. Lab., Hitachi Ltd., Tokyo, Japan

Volume

24

Issue

5

fYear

1989

fDate

10/1/1989 12:00:00 AM

Firstpage

1219

Lastpage

1225

Abstract

A 1-Mbit CMOS static RAM (SRAM) with a typical address access time of 9 ns has been developed. A high-speed sense amplifier circuit, consisting of a three-stage PMOS cross-coupled sense amplifier with a CMOS preamplifier, is the key to the fast access time. A parallel-word-access redundancy architecture, which causes no access time penalty, was also incorporated. A polysilicon PMOS load memory cell, which had a large on-current-to-off-current ratio, gave a much lower soft-error rate than a conventional high-resistance polysilicon load cell. The 1-Mbit SRAM, fabricated using a half-micrometer, triple-poly, and double-metal CMOS technology, operated at a single supply voltage of 5 V. An on-chip power supply converter was incorporated in the SRAM to supply a partial internal supply voltage of 4 V to the high-performance half-micrometer MOS transistors.

Keywords

CMOS integrated circuits; VLSI; integrated circuit technology; integrated memory circuits; random-access storage; 1 Mbit; 4 V; 5 V; 9 ns; CMOS; CMOS preamplifier; SRAM; address access time; cross-coupled sense amplifier; double-metal; on-chip power supply converter; parallel-word-access redundancy architecture; polysilicon PMOS load memory cell; single supply voltage; soft-error rate; static RAM; triple-poly; BiCMOS integrated circuits; CMOS memory circuits; CMOS technology; Helium; MOSFETs; Power supplies; Preamplifiers; Random access memory; Read-write memory; Redundancy; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.1989.572583

Filename

572583