A 3.5-ns, 500-mW, 16-kbit BiCMOS ECL RAM

Author

Suzuki, Makoto ; Tachibana, Suguru ; Watanabe, Atsuo ; Shukuri, Shoji ; Higuchi, Hisayuki ; Nagano, Takahiro ; Shimohigashi, Katsuhiro

Author_Institution

Central Res. Lab., Hitachi Ltd., Tokyo, Japan

Volume

24

Issue

5

fYear

1989

fDate

10/1/1989 12:00:00 AM

Firstpage

1233

Lastpage

1237

Abstract

A 16-kbit BiCMOS ECL SRAM with a typical address access time of 3.5 ns and 500-mW power dissipation was developed. The RAM was fabricated using half-micrometer, triple-poly, and triple-metal BiCMOS technology. The fast access time with moderate power dissipation has been achieved using new circuit techniques: a grounded-gate, nonlatching-type level converter with a wired-OR predecoder and a direct column sensing scheme having a cascode differential amplifier. As a result of extensive use of high-speed bipolar ECL circuits with self-aligned bipolar transistors, the RAM attains high-speed performance without degrading the low-power BiCMOS RAM characteristics.

Keywords

BIMOS integrated circuits; VLSI; emitter-coupled logic; integrated circuit technology; integrated memory circuits; random-access storage; 16 kbit; 3.5 ns; 500 mW; BiCMOS ECL SRAM; ECL circuits; address access time; cascode differential amplifier; circuit techniques; direct column sensing scheme; grounded-gate; power dissipation; self-aligned bipolar transistors; triple-metal; triple-poly; wired-OR predecoder; BiCMOS integrated circuits; Bipolar transistors; CMOS technology; Circuit synthesis; Degradation; Differential amplifiers; Driver circuits; Power dissipation; Random access memory; Read-write memory;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.1989.572586

Filename

572586