A 209 K-transistor ECL gate array with RAM

Author

Satoh, Hisayasu ; Nishimura, Takashi ; Tatsuki, Makoto ; Ohba, Atsushi ; Hine, Shiro ; Kuramitsu, Yoichi

Author_Institution

LSI Res. & Dev. Lab., Mitsubishi Electric Corp., Hyogo, Japan

Volume

24

Issue

5

fYear

1989

fDate

10/1/1989 12:00:00 AM

Firstpage

1275

Lastpage

1279

Abstract

A 12 K-gate ECL gate array with 36 kbit of dedicated RAM has been developed. An ECL logic cell structure with an extra transistor buried under a V_cc power bus is proposed to implement both the logic function and a memory cell. The logic part has the capability of implementing configurable RAM with up to 5.8 kbit. By employing 0.6- mu m double-polysilicon self-aligned technology, the intrinsic gate delay is 110 ps at a power consumption of 1.8 mW/gate. The address access times of dedicated RAM and configurable RAM are 3.0 and 1.8 ns, respectively. The gate array is applied to 9 K-gate logic circuitry with 35-kbit table look-aside buffer (TLB) memory using dedicated RAM and a 16-word*18-bit register file using configurable RAM.

Keywords

VLSI; bipolar integrated circuits; emitter-coupled logic; integrated circuit technology; logic arrays; random-access storage; 0.6 micron; 1.8 ns; 110 ps; 18 bit; 3 ns; 36 kbit; 5.8 kbit; ECL gate array; ECL logic cell structure; address access times; configurable RAM; dedicated RAM; double-polysilicon self-aligned technology; gate delay; memory cell; power consumption; register file; table look-aside buffer; Delay; Energy consumption; Information processing; Logic arrays; Logic circuits; Logic devices; Logic functions; Random access memory; Read-write memory; Registers; Wiring;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.1989.572595

Filename

572595