Title :
Multiple target clock distribution with arbitrary delay interconnects
Author :
Aguiar, R.L. ; Santos, D.M.
Author_Institution :
Dept. de Electron. e Telecoms, Aveiro Univ., Portugal
fDate :
10/29/1998 12:00:00 AM
Abstract :
A new technique is presented for multiple target clock distribution using controlled delay lines. This method is demonstrated to work with arbitrary delay lines. Simulations show that this method has strong advantages for cluster-level clock distribution, and can be applied to multichip interconnections
Keywords :
CMOS digital integrated circuits; delay lines; integrated circuit interconnections; multichip modules; timing; CMOS ICs; MCM; cluster-level clock distribution; controlled delay lines; delay interconnects; multichip interconnections; multiple target clock distribution;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19981520
