A 6.7-MFLOPS floating-point coprocessor with vector/matrix instructions

Author

Nakayama, Takashi ; Harigai, Hisao ; Kojima, Shingo ; Kaneko, Hiroaki ; Igarashi, Hatsuhide ; Toba, Tsuneo ; Yamagami, Yutaka ; Yano, Yoichi

Volume

24

Issue

5

fYear

1989

fDate

10/1/1989 12:00:00 AM

Firstpage

1324

Lastpage

1330

Abstract

An 80-bit floating-point coprocessor which implements 24 vector/matrix instructions and 22 mathematical functions is described. This processor can execute floating-point addition/rounding and pipelined multiplication concurrently, under the control of horizontal-type microinstructions. The SRT division method and CORDIC trigonometrical algorithm are used for a favorable cost/performance implementation. The performance of 6.7 MFLOPS in the vector-matrix multiplication at 20 MHz has been attained by the use of parallel operations. The vector/matrix instruction is about three times faster than conventional add and multiply instructions. The chip has been fabricated in 1.2- mu m double-metal layer CMOS process containing 433000 transistors on a 11.6*14.9-mm² die size.

Keywords

CMOS integrated circuits; VLSI; digital arithmetic; instruction sets; microprocessor chips; parallel architectures; pipeline processing; satellite computers; 1.2 micron; 20 MHz; 6.7 MFLOPS; 80 bit; CMOS process; CORDIC trigonometrical algorithm; SRT division method; VLSI microprocessor; double-metal layer; floating-point coprocessor; horizontal-type microinstructions; mathematical functions; parallel operations; pipelined multiplication; vector/matrix instructions; Application software; Associate members; CMOS process; Cache memory; Coprocessors; Costs; Graphics; Memory management; Microprocessors; Robot kinematics; Service robots; Workstations;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.1989.572608

Filename

572608