A 40-MFLOPS 32-bit floating-point processor with elastic pipeline scheme

Author

Komori, Shinji ; Takata, Hidehiro ; Tamura, Toshiyuki ; Asai, Fumiyasu ; Ohno, Takio ; Tomisawa, Osamu ; Yamasaki, Tetsuo ; Shima, Kenji ; Nishikawa, Hiroaki ; Terada, Hiroaki

Author_Institution

LSI Res. & Dev. Lab., Misubishi Electr. Corp., Hyogo, Japan

Volume

24

Issue

5

fYear

1989

fDate

10/1/1989 12:00:00 AM

Firstpage

1341

Lastpage

1347

Abstract

The authors present a 40-MFLOPS 32-bit floating-point processor (FP) which is a component chip for a data-driven single-board processor. The FP is the first practical LSI chip which has introduced the elastic pipeline scheme. All parts in the FP are autonomously controlled by self-timed circuits, and no system clock is needed for processing. The elastic pipeline scheme provides data buffering capability and stabilization of circuit operation at the same time. Pipelining has been extensively utilized so that high throughput over 40-MFLOPS can be achieved. An automatic power conservation technique, called ´latch mode control´, is also described.

Keywords

large scale integration; microprocessor chips; pipeline processing; 32 bit; 40 MFLOPS; LSI chip; automatic power conservation; component chip; data buffering capability; data-driven single-board processor; elastic pipeline scheme; floating-point processor; latch mode control; microprocessor; self-timed circuits; stabilization; Automatic control; Circuits; Clocks; Computer buffers; Control systems; Job shop scheduling; Laboratories; Large scale integration; Large-scale systems; Latches; Multiprocessing systems; Pipeline processing; Processor scheduling; Throughput;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.1989.572611

Filename

572611