• DocumentCode
    1467462
  • Title

    A 20-MIPS sustained 32-bit CMOS microprocessor with high ratio of sustained to peak performance

  • Author

    Jouppi, Norman P. ; Tang, Jeffrey Y F

  • Author_Institution
    Western Res. Lab., Digital Equipment Corp., Palo Alto, CA, USA
  • Volume
    24
  • Issue
    5
  • fYear
    1989
  • fDate
    10/1/1989 12:00:00 AM
  • Firstpage
    1348
  • Lastpage
    1359
  • Abstract
    The authors describe the design of a CPU chip with a high ratio of sustained system to peak performance (0.80). Attaining a high ratio of sustained system performance to peak performance avoids wasting circuit design effort at an architectural level through inefficient use of machine resources. The chip contains 180K transistors on a 6.98*8.73-mm2 die utilizing a 1.5- mu m CMOS process to obtain a sustained system performance of 20 MIPS. By keeping the design simple and regular both at an architectural and circuit level, and by using high-level tools on the complete design, a high sustained performance was obtained with relatively little design effort (2.5 man years).
  • Keywords
    CMOS integrated circuits; VLSI; circuit CAD; logic CAD; microprocessor chips; pipeline processing; 1.5 micron; 20 MIPS; 32 bit; CMOS microprocessor; CPU chip; VLSI chip; architectural level; circuit level; high-level tools; logic CAD; peak performance; performance ratio; pipeline design; sustained system performance; CMOS process; Central Processing Unit; Circuit synthesis; Clocks; Costs; Frequency; Hardware; Microprocessors; Reduced instruction set computing; System performance;
  • fLanguage
    English
  • Journal_Title
    Solid-State Circuits, IEEE Journal of
  • Publisher
    ieee
  • ISSN
    0018-9200
  • Type

    jour

  • DOI
    10.1109/JSSC.1989.572612
  • Filename
    572612