Analysis and modeling of on-chip high-voltage generator circuits for use in EEPROM circuits

Most of the presently available EEPROM circuits feature 5-V-only operation and therefore incorporate on-chip high-voltage generators. In spite of the importance of these latter circuits, a thorough analysis of the circuit has not been presented. In this paper the characteristics of the voltage multiplier circuit are thoroughly analyzed and modeled. The results obtained from this analysis are fully confirmed by experiments. The degradation characteristics of the circuit are discussed and its capability to compensate for nonvolatile memory degradation is shown.