DocumentCode
1467505
Title
Highly parallel residue arithmetic chip based on multiple-valued bidirectional current-mode logic
Author
Kameyama, Michitaka ; Sekibe, Tsutomu ; Higuchi, Tatsuo
Author_Institution
Dept. of Electron. Eng., Tohoku Univ., Sendai, Japan
Volume
24
Issue
5
fYear
1989
fDate
10/1/1989 12:00:00 AM
Firstpage
1404
Lastpage
1411
Abstract
Discusses the implementation of a residue arithmetic circuit using multiple-valued bidirectional current-mode MOS technology. Each residue digit is represented by new multiple-valued coding suitable for highly parallel computation. By the coding, mod mi multiplication can be simply performed by a shift operation. In mod mi addition, radix-5 signed-digit (SD) arithmetic is employed for a high degree of parallelism and multiple-operand addition, so that high-speed arithmetic operations can be achieved. Finally, the mod7 three-operand multiply adder is designed and fabricated as an integrated circuit based on 10- mu m CMOS technology.
Keywords
MOS integrated circuits; VLSI; digital arithmetic; integrated logic circuits; many-valued logics; parallel processing; 10 micron; CMOS; addition; bidirectional current-mode MOS technology; high-speed arithmetic operations; highly parallel computation; highly parallel residue arithmetic chip; mod7 three-operand multiply adder; multiple-operand addition; multiple-valued bidirectional current-mode logic; multiple-valued coding; multiplication; radix-5 signed-digit; residue arithmetic circuit; shift operation; Adders; Arithmetic; CMOS integrated circuits; CMOS logic circuits; CMOS technology; Concurrent computing; Integrated circuit technology; Logic; Logic circuits; Logic design; Parallel processing;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/JSSC.1989.572624
Filename
572624
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