A 10-ps resolution, process-insensitive timing generator IC

Author

Otsuji, Tai-Ichi ; Narumi, Naoki

Author_Institution

NTT LSI Labs., Kanagawa, Japan

Volume

24

Issue

5

fYear

1989

fDate

10/1/1989 12:00:00 AM

Firstpage

1412

Lastpage

1417

Abstract

Describes a novel circuit configuration and design technique for a high-speed timing generator IC with a 10-ps delay-time resolution. This circuit is composed of multistage delay units in matrix form. In each unit, delay time is finely controlled by loading transistor junction capacitance on an LCML inverter gate and is roughly done by the serial stage numbers of the gate. A dedicated delay-unit IC has been built by an Si bipolar process called SST-1A. The circuit demonstrates a high delay-time resolution of 10 ps at a clock rate of up to 1 GHz. Furthermore, an innovative process-insensitive design technique based on a polynomial formulation for the delay time is proposed. This will be effective in realizing a long delay circuit with high delay resolution.

Keywords

bipolar integrated circuits; delay circuits; emitter-coupled logic; integrated logic circuits; timing circuits; 1 GHz; LCML inverter gate; SST-1A; circuit configuration; clock rate; dedicated delay-unit IC; delay-time resolution; design technique; high-speed timing generator IC; loading transistor junction capacitance; long delay circuit; multistage delay units; polynomial formulation; process-insensitive design technique; process-insensitive timing generator IC; Bipolar integrated circuits; Capacitance; Carbon capture and storage; Circuits; Clocks; Delay effects; High speed integrated circuits; Inverters; Large scale integration; Polynomials; Process design; Propagation delay; Signal resolution; Timing; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.1989.572626

Filename

572626