• DocumentCode
    1467545
  • Title

    Behavior analysis of CMOS D flip-flops

  • Author

    Chao, Jonathan, II ; Johnston, Cesar A.

  • Author_Institution
    Bellcore, Morristown, NJ, USA
  • Volume
    24
  • Issue
    5
  • fYear
    1989
  • fDate
    10/1/1989 12:00:00 AM
  • Firstpage
    1454
  • Lastpage
    1458
  • Abstract
    The authors analyze two D flip-flops (DFF´s) generally considered to be the fastest (and most widely used), and compare their speed performance and their robustness against clock skew when a two-phase clocking scheme is applied. The effect of clock skew on their speed and proper logic operation is analyzed and verified with spice simulation.
  • Keywords
    CMOS integrated circuits; flip-flops; integrated logic circuits; CMOS D flip-flops; behaviour analysis; clock skew effects; dynamic D flip flops; logic operation; robustness against clock skew; speed performance; spice simulation; two-phase clocking scheme; Analytical models; CMOS logic circuits; Clocks; Delay; Flip-flops; Latches; Master-slave; Performance analysis; Robustness; SPICE; Silicon;
  • fLanguage
    English
  • Journal_Title
    Solid-State Circuits, IEEE Journal of
  • Publisher
    ieee
  • ISSN
    0018-9200
  • Type

    jour

  • DOI
    10.1109/JSSC.1989.572637
  • Filename
    572637
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1467545