High-resolution low-power CMOS D/A converter

Author

Yang, John W. ; Martin, Kenneth W.

Author_Institution

Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA

Volume

24

Issue

5

fYear

1989

fDate

10/1/1989 12:00:00 AM

Firstpage

1458

Lastpage

1461

Abstract

A very low-power, high-resolution, medium-speed D/A converter is described. The converter was realized using a standard analog CMOS technology. It achieved 15-bit monotonicity and less than 0.07-percent overall linearity at a clock frequency of 100 kHz, without requiring any trimming or calibration. The measured SNR was 85 dB, the power dissipation was less than 10 mW, and the distortion for a sinusoidal output was less than 0.04 percent. The D/A converter is intended for battery-powered speech and music synthesis applications where high dynamic range, low power, and low cost are all important.

Keywords

CMOS integrated circuits; digital-analogue conversion; integrated circuit technology; 10 mW; 100 kHz; 15 bit; 85 dB; D/A converter; DAC; SNR; battery-powered; clock frequency; distortion; high dynamic range; high-resolution; linearity; low cost; low-power; medium-speed; monotonicity; music synthesis; power dissipation; speech synthesis; standard analog CMOS technology; CMOS technology; Calibration; Clocks; Distortion measurement; Dynamic range; Frequency; Linearity; Power dissipation; Power measurement; Speech synthesis;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.1989.572638

Filename

572638