High-Reliability Trigate Poly-Si Channel Flash Memory Cell With Si-Nanocrystal Embedded Charge-Trapping Layer

Author

Chen, Hung-Bin ; Wu, Yung-Chun ; Chen, Lun-Chun ; Chiang, Ji-Hong ; Yang, Chao-Kan ; Chang, Chun-Yen

Author_Institution

Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan

Volume

33

Issue

4

fYear

2012

fDate

4/1/2012 12:00:00 AM

Firstpage

537

Lastpage

539

Abstract

This letter introduces a polycrystalline-silicon nanowire (NW) thin-film nonvolatile memory (NVM) with a self-assembled silicon-nanocrystal (Si-NC) embedded charge-trapping (CT) layer. This process is simple and compatible with conventional CMOS processes. Experimental results indicate that this NW NVM exhibits high reliability due to a deep-quantum-well structure and immunity of enhanced electric field underneath a disk-shaped Si-NC. After 10 000 P/E cycles, the memory window loss of the NVM with a Si-NC embedded CT layer is less than 12% until 104 s at 150 °C. Accordingly, a poly-Si thin-film transistor with a Si-NC embedded CT layer is highly promising for NVM applications.

Keywords

flash memories; random-access storage; semiconductor device reliability; CMOS process; deep-quantum-well structure; enhanced electric field; high reliability trigate poly-silicon channel flash memory cell; poly-silicon thin film transistor; polycrystalline-silicon nanowire; silicon-nanocrystal embedded charge-trapping layer; thin film nonvolatile memory; Logic gates; Nanocrystals; Nonvolatile memory; SONOS devices; Silicon; Transistors; Nanocrystal (NC); nonvolatile memory (NVM); thin-film transistor (TFT);

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/LED.2012.2184519

Filename

6168219